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The calendar provides the schedule of lectures, assignments, and handouts for the course. After the second quiz, the lectures and recitations are discontinued. The remainder of the sessions involve labs and project presentations by students in the course.

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Massachusetts Institute of Technology

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6.111 - ¼Æ¦ì¤Æ¨t²Î¹êÅç¾É½×

Department of Electrical Engineering and Computer Science
6.111 - Introductory Digital Systems Laboratory

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SCHEDULE FALL 2002

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All lectures (not quizzes) have lecture notes in addition to the handouts listed below.


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1 1 ²Ä¤@¤Ñ©Ò¥]¬A¨Æ¶µ¡G
First Day Packet includes:

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General Information

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Syllabus

¤@¯ëªº¹êÅç«Ç¸ê°T
General Laboratory Information

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Computer Information

²¤¶HPÅÞ¿è¤ÀªR»ö
Introduction to HP Logic

Analyzer
ªì¾ÇªÌ¾É½×
Beginner's Guide to WARP

¥iµ{¤Æ°}¦C¨Ï¥Î
PAL Programming

§@·~
Problem Set 1

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Lab 1

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Safety Memo

¦¨®M¤u¨ã
Kit Sign-out Form

­I´º¸ê®Æ
Background Information

©M®É¶¡ªí
and Schedule Form
6.111 ñ¦Wªí
6.111 Sign-up Sheet
¾É½×©M°ò¥»¥¬ªL
Introduction, Basic Boolean
2 2 ¹h¡B²Å¸¹©M¶×¬y±Æ
Gates, Symbols, and Busses
¥d¿Õ¹Ï
Kmap
½d¦C¡G¥d¿Õ¹Ï
Example, Kmaps
3 3 ¹h¡B¥¿¤Ï¾¹¡B«Ø¥ß¼Ò¶ô¡B
Gates, Flip Flops, Building Blocks,

­p¼Æ¾¹
Counters
4 4 VHDL
Negative True and VHDL
§@·~1 ¸Ñµª,§@·~2
PS 1 Solutions, PS 2
§@·~ 1
PS 1
­p¼Æ¾¹¡B¦³­­ª¬ºA¾÷
Counters, Finite State

¥iµ{¦¡¤Æ°}¦C
Machines, PALS
5 5 VHDL ¤¶²Ð¡F¹êÅé¡AGalaxy ®i¥Ü
VHDL Intro; Entities, Galaxy demo
6 6 ¹êÅç1
Lab 1
VHDL ´y­z
VHDL Statements
7 7 ¹êÅç2 (CPLD ©M 6264¸ê®Æªí)¡A§@·~3¡A§@·~2¸Ñµª
Lab 2 (CPLD and 6264 data sheets), PS 3, PS 2 Solutions
§@·~2
PS 2
VHDL ¦³­­ª¬ºA¾÷½d¨Ò¡A®É§Ç¡A¹êÅç2
VHDL FSM Example,Timing, Lab 2

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assignment
8 8 ³]­p¨BÆJ¡AVHDL¥]¡A
Design Procedure,VHDL Packages,

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Memories
9 9 ³ø§i«ü¾É¡A²Ä¤G¶¥¬qÀˬdªí¡A®Ñ¼g
Report Guide, Phase II form Checklist, Writing
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Style guide
²Ä¤G¶¥¬q³ø§i¡A²Ä¤@¦¸´úÅçÀ˰Q
Writing Phase II, Quiz 1 Review
10 Q1 ²Ä¤@¦¸´úÅç
QUIZ 1
²Ä¤@¦¸´úÅç (56-154, -169, -191)
QUIZ 1 (56-154, -169, -191)
11 10 §@·~3¸Ñµª
PS 3 Solutions
§@·~4
PS 4
§@·~3
PS 3
VHDL ºÊ©w¡A¥æ´¤¡A
VHDL Identifiers, Handshaking,

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Package examples
12 11 §@·~5¡A FPGA ¼Ò²Õ
PS 5, FPGA Module
¹êÅç2
Lab 2
³]­p³Ì«á´Á­­
Design Check-off
VHDLªº±Ô­z¡Aºâ¼ÆÅÞ¿è³æ¤¸
VHDL Statements, ALU example
13 12 §@·~4 ¸Ñµª
PS 4 Solutions
§@·~4
PS 4
¤G¦ì¤¸ºâ³N¡A±±¨î½d¨Ò(PI ±±¨î¾¹)
Binary Arithmetic, Control Example (PI controller)
14 13 ¹êÅç3
Lab 3
¹êÅç2
Lab 2
³Ì«á´Á­­
Check-off
¹ê²{¦h­Ó¦³­­ª¬ºA¾÷¦b
Implementation using multiple FSM's,
FLEX10k³¡¤À
FLEX10K parts
15 14 ¹êÅç3 ¤À¬£(®i¥Ü)
Lab 3 Assignment (demo)
16 15 §@·~5 ¸Ñµª
PS 5 solutions
¹êÅç2 ³ø§i¡A§@·~5ªº¹êÅç
L2 Report, PS 5 due in the lab
A/D¡AD/A¡A OP©ñ¤j¾¹(®i¥Ü)
A/D, D/A, Op Amps (demo)
17 16 Ãö©ó±MÃDªº¸ê°T
Project Information
±MÃD¶}©l
Project Kickoff
18 17 ±MÃD·§­n
Project Abstracts
¹êÅç3³]­p
Lab 3 Design
µø°T1
Video 1
19 18 MC6847 ¸ê®Æªí
MC6847 data sheet
µø°T2¡A¶Ç¿é½u(®i¥Ü)
Video 2, Transmission Lines (demo)
20 19 ¦p¦ó¨Ï§Aªº±MÃD¦¨¥\
How to Make Your Project Work
½s½X¾¹¡A°¨¹F¡A´úÅç2À˰Q
Encoders, Motors, Quiz 2 Review
21 ²Ä¤G©u
Q2
´úÅç2
Quiz 2
´£®×·|ij
Proposal Conferences
22 ¹êÅç3³Ì«á´Á­­
Lab 3 Check-off
23 ³]­p·|ij
Design Conferences
25 ¹êÅç3³ø§i
Lab 3 Report
26 ±MÃD³]­p²³ø
Project Design Presentations
27 ¤¶²Ð±MÃD³]­p
Project Design Presentations
28 ±MÃD³]­p²³ø
Project Design Presentations
29 ±MÃD³]­p²³ø
Project Design Presentations
30 ±MÃD²³ø
Project Presentations
31 ¿ý»s±MÃD®i¥Ü
Video-taping the Project Demonstrations
32 ±MÃD³ø§iºI¤î¤é
Project Reports due



 
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