许多软件工具都能被用来导入.dat文件。
Any number of software tools can be used to import the .dat files in this section.
本页内容已获Francis A. Honore.授权提供。
Contents of this page courtesy of Francis A. Honore. Used with permission.
PAL 编程
PAL Programming
Verilog® 仿真
Verilog® Simulation
创建和仿真RAM
Creating and Simulating RAM
ROM初始化
ROM Initialization
PROM工具
PROM Tools
PAL编程
PAL Programming
Cypress公司的WARP是一种产生PAL编程数据的工具。WARP使用Verilog®语言描述的设计，生成一个JEDEC（.jed）编程文件，提供给PAL烧片器使用。要在实验室电脑上使用WARP，点击桌面上的Galaxy图标起动应用程序。Galaxy是WARP的图形前端。关于使用WARP的指导，请参考WARP指南.
Cypress WARP is a tool for generating PAL programming data. WARP takes a design in Verilog® and produces a JEDEC (.jed) programming file to be used by the PAL burners.To use WARP on the Lab PC, launch the application by clicking on the Galaxy desktop icon. Galaxy is the graphical front end to WARP. For instructions on using WARP, refer to theWARP Tutorial. (PDF)
一旦创建好了一个.jed文件,需要将其转化成PAL编程配置以烧入PAL.关于编程器使用的指导,参阅PAL编程器指南.
Once a .jed file is created, it needs to be transferred to the PAL programming station to be burned into the PAL. For instructions on using the PAL programmer, view the PAL Programmer Guide. (PDF)
Altera FPGA 编程
Altera FPGA Programming
生成Altera FPGA的编程文件的过程可以被分成两个阶段: Verilog®硬件描述的仿真和验证,之后是合成和优化.ModelSim将被用于对被建系统的Verilog®描述进行仿真.Altera的MAX+plusII工具执行最后阶段的工作,把Verilog®描述映射到器件中去. MAX+plusII也具有内建的仿真器.
The two phases for generating a programming file for the Altera FPGA's can be split between simulation/verification of the Verilog® hardware description followed by synthesis/optimization. Modelsim will be used for simulating the Verilog® description of the system to be built. Altera's MAX+plusII tool performs the final phase of mapping the Verilog® description to the device. MAX+plusII also has a built-in simulator.
ModelSim入门
Starting ModelSim
在使用Windows? XP的实验室电脑上,从桌面图标起动ModelSim(或者开始->所有程序->ModelSim SE->ModelSim)
On the Lab PC under Windows® XP, launch ModelSim from the Desktop icon (or Start -> All Programs -> ModelSim SE -> ModelSim)
在SUN的工作站上时，必须先正确配置你的环境。然后运行’vsim&’来启动应用程序.
On a Sun workstation, you must first configure your environment correctly. Then run 'vsim &' to start the application.
创建一个新的工程:文件->新建->工程,之后会有向导引导你一步步完成工程创建.
Create a new project with: File->New->Project and a wizard walks you through project creation.
关于使用Modelsim 仿真Verilog®的例子,请参考ModelSim指南.
For examples of using Modelsim for Verilog® simulation, refer to the Modelsim tutorial. (PDF)
在ModelSim中创建和仿真RAM
Creating and Simulating RAM in ModelSim
参阅这部分指南来在MAX+plusII中生成存储器并在ModelSim中仿真.(PDF)
Refer to this guide to generate memories in MAX+plusII and simulate in Modelsim. (PDF)
为MAX+plusII生成ROM数据
Generating ROM Data for MAX+plusII
当在Altera FPGA中生成一个内部ROM时，存储器内容能够在存储器初始化文件（.mif）中得到说明。这种格式在这里给出，并可以用 (rom8x8.mif (MIF)) 作为起点。用这个文件和megawizard 插件程序管理器，创建一个ROM块，在设计中具体举例说明。
When generating an internal ROM in an Altera FPGA, the memory contents can be specified in a Memory Initialization File (.mif). The format is shown here and also available (rom8x8.mif (MIF)) as a starting point. This file is used with the Megawizard Plug-in Manager to create a ROM module to instantiate in a design.
-- MEMORY INITIALIZATION FILE
-- EXAMPLE DATA FOR AN 8x8 ROM
WIDTH = 8; % WIDTH OF OUTPUT IS REQUIRED, ENTER A DECIMAL VALUE %
DEPTH = 8; % DEPTH OF MEMORY IS REQUIRED, ENTER A DECIMAL VALUE %
ADDRESS_RADIX = HEX; % Address and data radixes are optional, default is hex %
DATA_RADIX = HEX; % Valid radixes = BIN,DEC,HEX or OCT %
CONTENT BEGIN
0 : 07; % ADDRESS : VALUE %
1 : 06;
2 : 05;
3 : 04;
4 : 03;
5 : 02;
6 : 01;
7 : 00;
END;
-- SHORTCUTS FOR SPECIFYING CONTENTS
-- [0..FF] : 0; % Range--Every address from 0 to FF = 0%
-- D : 7; % Single address--Address D = 7 %
-- 6 : 9 C 8; % Range starting from specific address--%
-- If there are multiple values for the same address only the last value is used
为生成ROM模块，采用了MAX+plusII中的这个例子：
To generate a ROM module using this example in MAX+plusII:
- 1．文件->MegaWizard Plug-In Manager
File -> MegaWizard Plug-In Manager
- 2．选择“Create a new custom megafunction variation”
Select "Create a new custom megafunction variation"
- 3．单击Next
Click Next
- 4. 选择Verilog® HDL
Select Verilog® HDL
- 5. 选择storage -> LPM_ROM
Select storage -> LPM_ROM
- 6. 输入一个输出名，如“rom8x8”
Enter an output name such as "rom8x8"
- 7. 单击Next
Click Next
- 8. 在这个例子里选择’3’作为输出q的宽度
Select '3' for width of q output for this example
- 9．不检查”Which ports should be registered”下的’address input port’
Uncheck 'address input port' under "Which ports should be registered?"
- 10.单击Next
Click Next
- 11.浏览生成的或从上面下载下来的rom8x8.mif文件
Browse to the rom8x8.mif file that was created or downloaded from above
- 12.单击Next
Click Next
- 13.一页摘要显示将要创建的文件
A summary page shows the files to be created
- 14.单击Finish
Click Finish
生成PROM数据
Generating PROM Data
有一组用来生成数据的命令行工具,生成的数据会存储在PROM芯片里.这些工具仅在final专题中需要使用,例如,可能用到PROM来存储字符或者图像数据.PROM工具指南中提供了更多的相关细节.
There are a suite of command line tools available for generating data to be stored in PROM chips. These tools are only needed for final projects which, for example, may use PROMs for storing character or image data. A promtools guide provides further details.
Dat2ntl是个命令行程序,用来生成.hex(.ntl)文件,这种文件也适于MAX+plusII初始化ROM.
Dat2ntl is a command line routine for generating a .hex (.ntl) file which is also suitable for MAX+plusII ROM initialization.
仿效impulses.dat中的例子创建一个.dat文件.(DAT)转换到Intel Hex格式:’dat2ntl impulses.dat impulses.ntl’
Create a .dat file following the example in impulses.dat. (DAT) Convert to the Intel Hex Format: 'dat2ntl impulses.dat impulses.ntl'.
更多的相关细节参考dat2ntl manpage.(PDF)
Refer to the dat2ntl manpage for further details. (PDF)
