负责讲师
Anantha Chandrakasan教授
授课员
Anantha Chandrakasan教授
Donald E. Troxel教授
推荐读物
推荐下列图书。不要求购买。
逻辑设计
Katz, Randy H. 《现代逻辑设计》 Addison Wesley, 1993. ISBN: 0201308576.
Verilog®
有很多好的Verilog®的书。我们强烈建议你采用一本Verilog®的书，下面给出两本推荐的书
Palnitkar, Samir. 《Verilog® HDL》. 第二版 Pearson Education, 2003. ISBN: 0130449113.
Thomas, Donald, 和 Philip Moorby. 《Verilog®硬件描述语言，第五版》 5th ed. Kluwer Academic Publishers, 2002. ISBN: 1402070896.
器件管脚/资料
在网上大多数器件的管脚都能查得到。我们会在课程网页上张贴出大多数相关的实验需要的器件资料。
制图模板
测试中你不需要使用模板来绘制逻辑图。本课程中提交的所有逻辑图必须使用模板或在电脑上绘制，除非测试，测试时要求的仅是图清晰易读。对于课后作业和实验预习，你可以使用绘图模板，但你很可能使用基于电脑的绘图包。建议的模板：MIL-STD-806C, in 1/2, 3/8 or 3/4 size, Koh-I-Noor No. 830544或者是《快速设计》或Pickett的課本.
课程的进行
课程
在学期的最初两周内，将会有三分之一的讲课，而不是复习课（为了快速地增加和说明实验1所需要的材料）。在此之后，会提供3个并行的复习部分（为了减小班级规模）。讲课和复习在学期期末将会停止，从而你能够集中准备期末专题（详情参阅课程日历）。我们将和你频繁地在实验室里见面。在结构框图会议之后我们将会在举办专题组报告的讲堂里见面.专题报告的详细通知会被发给学生。
作业
会布置3次作业，你的解答会被评分；题目来源于讲课和复习课。作业的目的是加强讲课/复习材料，并帮你预习实验。
实验作业
所有的实验练习必须完成；这是为了使你期末能进入学期专题中。在练习时，每个学生独立完成。
测验
学期中会有一次测验。
学期专题
最重要的作业是学期专题，下面你将会得到关于学期专题的更详细的指导。在进行学期专题时，你要与一个或者至多两个搭档合作。你必须在学期初开始寻找你的搭档。
评分方法
作业迟交会被处罚。不会接受迟交的课后作业。在应缴日期后的1-5个工作日完成实验室作业会受到每天扣20%的处罚。迟交作业超过5天将不可原谅，不会给予分数。
实验1检查单将由教学助教或者实验助教签核,并包含你的报告.注意:检查单不是报告.网站上给出了实验1报告模板
实验2报告会被作为申请CIM材料的一部分.讲座中将会给出更详细的信息.实验2检查单和期末报告的截止日期在同一天.
实验3具有中间检查单, 其最后的检查单和报告的截止日期在同一天.事实上,不需要依据你实验情况对报告作修改.但是,没有实验结果的报告会得0分.
学期专题要求必须根据指导上给出的时间表完成;你必须在逻辑图会议后对班上的其他同学就你的专题部分作报告.你必须展示(即报告)你的学期专题,即使它还没有完全实现功能,并且必须上交书面报告以获得及格分数.
等级分(A,B,C,D,F)的评定是不可避免的主观过程.但是,我们会采用量化数据.从成绩加权可以算出一个单一的数值.依据下面的权值
| 测验 |
10% |
| 书面(实验2修订本--MIT本科交流要求的一部分) |
10% |
| 作业（强调实验思想） |
5% |
| 出勤（讲座，复习，实验） |
5% |
| 实验1 |
10% |
| 实验2 |
10% |
| 实验3 |
15% |
| 期末专题 |
35% |
|
我们为这些大致的数字建了一个柱状图，讨论所有学生的个人表现。考虑的一些因素是：
- 通过完成大多数作业以及在期末专题期间在实验室的出勤的情况反映出的个人努力。
- 实验2和实验3的完成情况。一个学生不完成实验3而获得A，这在过去的历史上还是非常少见的。当然，即使做了实验3，也有可能获得低于A的成绩。
- 专题表现
- 没有拿出期末专题报告的学生会得到分数F
- 不制作专题的学生会得到分数F
- 在区分A和B时，专题复杂度是一个重要因素。如果期末专题不如最后实验复杂，几乎不会得A.
- 一个学生没有完成期末专题而获得A是相当困难的。当然，也有可能即使完成了期末专题也仅得低于A的成绩。
虽然6.111具有重要的课堂部分，它首先是个实验课题。在实验室里完成实验比其他部分更重要。课堂部分被看作实验部分的支持。讲座涉及的一些材料会与高级的主题相关（功率耗散，映射到ASIC设计，测试，等等）。一些内容可能在期末专题上用不上，但却是当今工业中新兴的重要数字系统问题。
以往，6.111中的平均成绩水平和平均表现都相当高。一大批学生做出了”A”等水平的作业也确实获得了A的成绩。可以推知,即既然平均表现等级这么高,缺掉本课程的任意部分,即使是作业,都会导致令你失望的成绩.保持努力,是很重要的.
最后,令人遗憾的是,我们要提一下在6.111 中对学术诚实的期望，这非常重要。 这么做，不是因为我们认为你们中有人不诚实，也不是侮辱你的智力或者人格，而是避免任何误会。
首先，测验是个人的努力。 作业和实验练习将也是个人的努力。 不过，问问题，从我们、同学或者其他任何人得到帮助是可以的。 但题目要自己做。合作的迹象是不允许的，例如相同的代码或者抄袭的数据，会得到近乎严厉的处罚。教学助教会持续问你解答中的问题，以确认你理解自己的解答过程。
最后的专题与之不同。 我们确实希望你能与课程教员、你的同学，特别是你的实验伙伴合作。 合写或是个人的报告都是允许的，但是合写报告的情况下指明每部分工作的责任人很重要。
实验课
阅读通用实验知识讲义(PDF) 在你在实验室做的任何作品上签名，没有做的不要签。否则下次你来的时候它可能无法还原。
时间表
讲课和作业的时间表包含在这个数据包中，在课程网站上也有（且会定期更新）。在这个课程里遵照时间表是非常重要， 以准备好做学期专题---在6.111中最重要的一项工作。 假如你准备合适，学习过程将是非常令人愉快的。
6.111的额外的单元
许多6.111的学生每周花的时间比预批的12个单位额定时还多。主要是因为工作量大的期末专题。现在可以注册6.905，并且为6.111获得增加的6个单位的学分。你6.905的分数会与6.111的分数相同。6.111的分数不会受到注册6.905影响。
我们准许额外单元的目的有两方面。首先是我们想让6.111的学生明白他们不需要完成比过去工作量更大、更复杂的专题。其次，认识到仍会有许多学生做雄心勃勃的专题，我们想给这些6。111的学生根据与其工作付出相称的单元数给与学分。注册额外单元的过程将会在学期晚些时候宣布。
决定分数和专题所需时间固然都是主观的。最后一个实验课提供一些对估计专题的工作量和复杂度的指导。关于6.111合理的专题规模的合理性准则是每个人仅需要一组套件和电路板。
6.111的学生专题常因为学生想要实现并行和高速的运算功能而变得过于庞大。数据通道常常过宽和多余。通常更好的是使数据通道形式和宽度最小化，即使这会导致更为复杂的控制线路
用PAL和FPGA实现的FSM允许执行复杂的控制。 请记住庞大的数据通道不是好的设计，即使它能提供比需要快得多的运算速度！花更多的时间思考，更少的时间接线，几乎总是更好的。
Instructor In-charge
Prof. Anantha Chandrakasan
Lecturers
Prof. Anantha Chandrakasan
Prof. Donald E. Troxel
Recommended Reading
The following books are recommended. Purchase is not required.
Logic Design
Katz, Randy H. Contemporary Logic Design. Addison Wesley, 1993. ISBN: 0201308576.
Verilog®
There are plenty of good Verilog® books. We strongly recommend that you get a Verilog® book. A couple of suggestions are given below:
Palnitkar, Samir. Verilog® HDL. 2nd ed. Pearson Education, 2003. ISBN: 0130449113.
Thomas, Donald, and Philip Moorby. The Verilog® Hardware Description Language. 5th ed. Kluwer Academic Publishers, 2002. ISBN: 1402070896.
Component Pinouts/Data
Pinouts for most components easily available through the web. We will post most of the relevant sheets needed for the labs on the course web site.
Drawing Template
You do not have to use a template for drawing logic diagrams on the quiz. All logic diagrams submitted in this subject must be drawn with a template or on a computer, except for the quiz, where all that is required is that logic diagrams be legible. For homework and lab preparation, you may use a drawing template, though it is likely that you will use a computer-based drawing package. Preferred templates: MIL-STD-806C, in 1/2, 3/8 or 3/4 size, Koh-I-Noor No. 830544 or equivalent in Rapid Design or Pickett.
Conduct of the Subject
Classes
In the first couple of weeks of the term, there will be a third weekly lecture instead of a recitation (to quickly ramp up on material needed for Lab 1). After this period, three parallel recitation sections will be offered (to reduce class size). Lectures and recitations are discontinued at the end of the term so you can focus on the final project (see course calendar for details). We will meet you frequently in the laboratory. We will meet in the lecture hall for project group presentations after the block diagram conferences. Notification of particulars of the project presentations will be sent to students.
Problem Sets
Three problem sets will be assigned and your solutions will be graded; these are based on the lectures and recitations. The goal of the problem sets is to reinforce lecture/recitation material and help prepare you for the labs.
Laboratory Assignments
All laboratory exercises must be completed; these are intended to prepare you for the term project. In doing these exercises, each student works individually.
Quiz
There will be one quiz during the term.
Term Project
The most important assignment is the Term Project, about which you will receive more detailed instruction later. In doing this assignment, you will work with one or, at most, two partners. You should begin finding your partner(s) early in the term.
Grading Policy
Late work will be penalized. Late homework will not be accepted. Lateness of the lab assignments will result in a 20% per day penalty for work completed 1-5 working days after the due date. No point credit will be given for unexcused lateness exceeding 5 days.
The Lab 1 Checkoff sheet is to be initialed by a teaching assistant ("TA") or laboratory assistant ("LA") and included with your report. Note that the checkoff sheet is not the report. Lab 1 report template is posted on the web site.
Lab 2 report will be used for part of the CIM requirement. More details will provided in lecture. Lab 2 checkoff and final report are due on the same day.
Lab 3 has an intermediate checkoff and the final checkoff and report are due on the same day. There is virtually no modification required to a report depending on the working of your lab implementation. However, reports with no lab effort will receive a zero.
The term project requirements must be completed in accordance with the schedule given in the instructions. You must make a presentation of your part of your project to the rest of the class after the logic diagram conference. You must demonstrate (i.e., present) your term project even if it does not fully function, and you must submit the written report in order to receive a passing grade.
The assignment of letter grades (A, B, C, D, F) is an inherently subjective process. We do, however, make use of numerical data. A single number is computed by weighting graded assignments. The following weights will be used:
| Quiz |
10% |
| Writing (Lab 2 revision- part of the MIT undergraduate communication requirement) |
10% |
| Problem Sets (emphasis on lab concepts) |
5% |
| Participation (lectures, recitations, labs) |
5% |
| Lab 1 |
10% |
| Lab 2 |
10% |
| Lab 3 |
15% |
| Final Project |
35% |
|
We construct a histogram of these summary numbers and proceed to discuss individual performances of virtually all students. Some of the factors considered are:
- Diligence as measured by completion of most of the problem sets and by presence in the laboratory during final project time.
- Completion of Labs 2 and 3. Past history has been that it is extremely rare for a student to receive an A without completing Lab 3. Of course, it is possible to get a grade lower than an A even if Lab 3 is done.
- Project performance.
- Any student who does not turn in a final project report will receive an F.
- Students who do not construct a project will receive an F.
- Project complexity is an important factor in discriminating between an A and a B. An A is rarely given if the final project is not as complicated as the last Lab.
- It is extremely difficult for a student to receive an A without completing the final project. Of course, it is possible to get a grade lower than an A even if the final project is completed.
Although 6.111 has a significant classroom component, it is primarily a lab subject. Accomplishments in the lab tend to be weighted more heavily than other components. The classroom component is viewed as supportive of the lab components. Some material covered in lectures will be related to advanced topics (power dissipation, mapping to ASICs, testing, etc.). Some the concepts might not be applicable to your final project but are important emerging digital system issues in industry today.
Traditionally, both average grade levels and average performance have been quite high in 6.111. A large number of students do "A" level work and are, indeed, rewarded with a grade of A. The corollary to this is that, since average performance levels are so high, skipping any part of the subject, even the problem sets, can lead to a disappointing grade. It is important that you keep up with the work.
Finally, and unfortunately, it is important for us to outline our expectations for academic honesty in 6.111. We do this not because we expect any of you to be dishonest, nor to insult your intelligence or character, but to avoid any misunderstandings.
First, the quiz is to be an individual effort. The problem sets and lab exercises are also to be individual efforts. However, it is okay to ask questions, get help from us, fellow students, or anyone else. But then, do them by yourself. Indications of collaboration such as incidents of identical code or copied figures are unacceptable and are liable to be dealt with in a seemingly harsh fashion. The TA's will be asking you about your solutions to make sure you really do understand what you have done.
The Final Project is a different story. We do expect you to collaborate, with the course staff and with your fellow students, especially with your lab partner. Joint or individual reports are acceptable, but in the case of joint reports it is important that responsibility for each section of the work be indicated.
Laboratory
Read the General Laboratory Information (PDF) handout. Put your name on anything that you build in the laboratory and leave unattended. Otherwise, it may be gone when you return.
Schedule
The schedule of the lectures and assignments is in this packet. The schedule of the lectures and assignments is posted (and will be updated regularly) on the course website. Staying on schedule is very important in this subject, in order to be prepared to do the term project, which is the single most important assignment in 6.111. It will be an enjoyable experience if you are properly prepared.
Extra Units for 6.111
Many 6.111 students spend more hours per week than warranted by the 12 unit rating. Primarily this is due to large final projects. It is now possible to register for 6.905 and gain an additional 6 units of credit for 6.111. Your grade for 6.905 will be the same as your grade for 6.111. Your grade for 6.111 is not influenced by registration for 6.905.
Our motivation for enabling the availability of these extra units is two-fold. Foremost is our desire to convince 6.111 students that they need not do a project which is bigger and more complicated than ever done in the past. Secondly, recognizing that many students will continue to do ambitious projects, we would like to credit 6.111 students with units appropriate to work expended. Procedures for registering for the extra units will be announced later on in the term.
Both the determination of grades and the project time requirements are inherently subjective. The last Lab provides some guidance to the evaluation of project size and complexity. A reasonable guideline as to size of 6.111 projects is that it not require more than a kit and a proto board per person.
6.111 student projects often become too large because of a desire to effect computations in parallel and at high speed. Data paths are often unnecessarily wide and redundant. It is generally far better to minimize the type and extent of the data paths even though this results in more complicated control circuitry.
FSMs implemented with PALs and FPGAs allow implementation of complicated control. Please remember that massive data paths that enable computation at speeds far faster than needed do not represent a good design! It is almost always better to spend more time thinking and less time wiring.
