麻省理工学院“开放式课程网页” | 电机工程与计算机科学 | 6.111 2004春季课程：数位系统概论实验

下面的日历给出了本课程讲课(L),复习课(R),专题课(P)的资讯。最后的讲课或复习课学期结束前5个星期上完；在此之后，课程时间全部投入到期末专题中。
The calendar below provides information on the course's lectures (L), recitations (R), and project (P) sessions. The last lecture or recitation is delivered 5 weeks before the end of the semester; after that date, class time is spent entirely on the final project.

课	课程单元	重要日期
讲课1 L1	介绍 Introduction 课程目标，数字逻辑，硬件描述语言 Course Objectives, Digital Logic, Hardware Description Languages 在实验室由教学助教演示逻辑分析仪教程 Logic Analyzer Demos in the Lab by TAs	作业1 Problem Set 1 Out 实验1 Lab 1 Out
讲课2 L2	组合逻辑 Combinational Logic 逻辑门，布尔代数，布尔代数的可视化，风险 Logic Gates, Boolean Algebra, Visualizations of Boolean Algebra, Hazards 在实验室由教学助教演示逻辑分析仪教程（续） Logic Analyzer Demos in the Lab by TAs (cont.)
讲课3 L3	Verilog®导论（组合逻辑） Introduction to Verilog®(Combinational Logic) 逻辑综合，Verilog®硬件描述语言，用Verilog®描述组合逻辑，测试板 Logic Synthesis, The Verilog® Hardware Description Language, Combinational Logic in Verilog®, Testbenches
讲课4 L4	时序搭建模块 Sequential Building Blocks 用反馈、锁存器和触发器保存状态，时钟和时序限制，时钟脉冲相位差 Preserving State with Feedback, Latches and Flip-flops, Clocks and Timing Constraints, Clock Skew 在实验室由教学助教演示WARP、MAX+plus II、ModelSim教程 WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs
讲课5 L5	简单时序电路及Verilog® Simple Sequential Circuits and Verilog® 简单计数器、时序电路的Verilog®实现 Simple Counters, Verilog® Implementation of Sequential Circuits 在实验室由教学助教演示WARP、MAX+plus II、ModelSim教程(续) WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs (cont.)	作业1到期 Problem Set 1 Due
讲课6 L6	有限状态机及Verilog®实现 Finite-State Machines and Verilog® Implementation 亚稳态和同步，Mealy和Moore形式，Verilog®实现， FSM实例 Metastability and Synchronization, Mealy and Moore Formalisms, Verilog® Implementations, FSM Examples	作业2Problem Set 2 Out 实验2 Lab 2 Out
复习课1 R1	实验2讨论和演示 Lab 2 Discussion and Demonstration	实验1检查 Lab 1 Checkoff 实验1报告到期 Lab 1 Report Due
讲课7 L7	存储器 Memories RAM和ROM的工艺和类型，存储器控制器电路，专用存储器，高性能接口 Technologies, Types of RAM and ROM, Memory Controller Circuits, Specialty Memories, High-performance Interfaces
讲课8 L8	算术电路 Circuits for Arithmetic 二进制加减法，全加器实现及其性能，高速加法，带符号算术运算 Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic
复习课2 R2	复习课 Recitation	作业2到期 Problem Set 2 Due
讲课9 L9	模拟构建模块 Analog Building Blocks 模拟输入、高效Op-amp电路、A/D和D/A转换、高效A/D和D/A电路 Analog Inputs, Useful Op-amp Circuits, A/D and D/A Conversion, Useful A/D and D/A Circuits
讲课10 L10	系统集成发布和主/副FSM System Integration Issues and Major/Minor FSM 层次和模块，数据和控制通道，主/副FSM, Altera的存储器模块（RAM/ROM），设计技巧 Hierarchy and Modularity, Data and Control Paths, Major and Minor FSMs, Memory Modules (RAM/ROM) in Altera, Design Tips 实验3概述 Lab 3 Overview	作业3 Problem Set 3 Out
复习课3 R3	复习 Recitation	实验2检查 Lab 2 Checkoff
讲课11 L11	可重复配置逻辑 Reconfigurable Logic 商用器件概述，可编程逻辑(PAL),FPGA架构，软件工具 Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools	实验2报告到期 Lab 2 Report Due 实验3 Lab 3 Out
讲课12 L12	可重复配置逻辑（续） Reconfigurable Logic (cont.) 商用器件概述，可编程逻辑(PAL),FPGA架构，软件工具 Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools
复习课4 R4	复习 Recitation
讲课13 L13	视频 Video 显示，同步，信号恢复，同步时序 Displays, Synchronization, Recovery of Signals, Sync Timing
讲课14 L14	专题开始 Project Kickoff 以往6.111专题的视频，专题创意，检查和目标，专题指导，评分，异步接口，器件对器件通讯 Video of Past 6.111 Projects, Project Ideas, Deadlines and Goals, Project Guidelines, Grading, Asynchronous Interfaces and Kit-to-kit Communication
	无复习课 No Recitation	实验3模拟检查 Lab 3 Analog Checkoff 作业3到期 Problem Set 3 Due
讲课15 L15	数字集成电路和系统 Digital Integrated Circuits and Systems Moore定律，VLSI集成，布线，制造，专用应用电路，微处理器，状态和运算传递，重计时，并行和流水线操作 Moore's Law, VLSI Integration, Layout and Fabrication, Application-specific Circuits, Microprocessors. Behavioral and Algorithmic Transformations, Retiming, Parallelism and Pipelinling	教学助教特别测验复习 Special Quiz Review by TAs 组成专题小组 Formation of Project Teams
复习课5 R5	复习 Recitation
讲课16 L16	功率耗散 Power Dissipation 热量和电池寿命问题,能源消耗,针对能源的电路和运算优化,电压换算 Heat and Battery Life Issues, Sources of Power Dissipation, Circuit and Algorithm Optimizations for Power, Voltage Scaling	专题摘要到期 Project Abstracts Due 实验3检查 Lab 3 Checkoff 实验3报告到期 Lab 3 Report Due
讲课17 L17	电机与位置测定 Motors and Position Determination 伺服,位置测量,编码,电机,绕组 Servos, Position Measurement, Encoders, Motors, Windings	为提案会议准备的专题提案到期 Project Proposals for Proposal Conference Due
专题课1 P1	与教学助教的提案会议 Proposal Conference with TAs	实验2校定报告到期 (麻省理工本科沟通要求的一部分) Lab 2 Revised Report Due (part of the MIT undergraduate communication requirement) 为提案会议准备的专题提案到期 Project Proposals for Proposal Conference Due
专题课2 P2	与教学助教的结构图会议 Block Diagram Conference with TAs
专题课3 P3	与教学助教的结构图会议（续） Block Diagram Conference with TAs (cont.)
专题课4 P4	与教学助教的结构图会议（续） Block Diagram Conference with TAs (cont.)
专题课5 P5	专题设计报告 Project Design Presentations	HKN复习 Eta Kappa Nu ("HKN") Review 定制专题审核单到期 Customized Project Checklist Due
专题课6 P6	专题设计报告（续） Project Design Presentations (cont.)
专题课7 P7	专题设计报告（续） Project Design Presentations (cont.)
专题课8 P8	专题设计报告（续） Project Design Presentations (cont.)
专题课9 P9	专题设计报告（续） Implement/Debug
专题课10 P10	实现/调试 Implement/Debug (cont.)
专题课11 P11	实现/调试(续) Implement/Debug (cont.)
专题课12 P12	实现/调试(续) Implement/Debug (cont.)
专题课13 P13	实现/调试(续) Implement/Debug (cont.)
专题课14 P14	期末专题展示 Final Project Demonstrations	期末专题报告截止(专题课13后3天) Final Project Report Due (three days after session P13)